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    • 专利摘要:
    The invention relates to an artificial neuron for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight. The artificial neuron includes a read circuit and an integration circuit. The integration circuit (CI) comprises a synaptic weight accumulator (ACC) at the terminals of which a membrane voltage is established (Vmem) and a comparator configured to emit a postsynaptic pulse in the event of a threshold being crossed by the voltage membrane. The reading circuit (CL) is configured to impose a reading voltage independent of the membrane voltage on the synapse and to provide the integration circuit with an analog quantity representative of the synaptic weight (PSa). Figure for the abstract: Figure 5
    公开号:FR3089663A1
    申请号:FR1872515
    申请日:2018-12-07
    公开日:2020-06-12
    发明作者:François Rummens；Alexandre VALENTIAN
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Description
    Title of the invention: Artificial neuron for neuromorphic chip with resistive synapses
    Technical area
    The field of the invention is that of neuromorphic chips with artificial neural networks exploiting synapses with resistive memory.
    Prior art
    A nerve cell, or neuron, can be broken down into several parts:
    - The dendrites which are the inputs of the neuron via which it receives signals of excitation or inhibition;
    - The body of the neuron which is the scene of ionic exchanges through the cell membrane;
    - The axon, a long extension of the cell body, which is the only exit from the body.
    Depending on the excitation or inhibition signals received at the dendrites, ions pass through the cell membrane. The imbalance of charges between the inside and the outside of the cell induces a difference in tension on both sides of the membrane. This is called membrane voltage across a membrane capacitor. When this membrane tension exceeds a certain level, that is to say when the cell is sufficiently excited, the neuron experiences a brutal exchange of ions. This results in a significant variation in the membrane tension. This variation, called action potential ("action potential" or "spike" in English), propagates along the axon, towards the synaptic buttons which constitute the outputs of the neuron. Viewed from outside the cell, these "spikes" constitute the electrical activity of the neuron.
    [0004] In a network of biological neurons, each neuron is connected to several thousands of others via as many synapses. The term synapse designates the connection between the axon termination of a so-called presynaptic neuron and a dendrite of a so-called postsynaptic neuron. The influence of the presynaptic neuron on the postsynaptic neuron is balanced by the weight of the synapse, which can be excitatory or inhibitory. In the first case, a presynaptic spike charges the membrane tension of the postsynaptic neuron and precipitates the generation of a postsynaptic action potential. In the second case, a presynaptic spike has the effect of depolarizing the postsynaptic membrane and delaying the onset of a postsynaptic action potential.
    [0005] Artificial neural networks are used in various fields of signal processing such as for example in data classification, image recognition or decision-making. They are inspired by the biological neural networks of which they imitate the functioning and are essentially composed of artificial neurons interconnected by synapses which can be implemented by resistive components whose conductance varies according to the voltage applied to their terminals.
    Due to their high density and their non-volatile nature, these resistive components (memristors or RRAM) are ideal candidates for the implementation of synapses. The variable resistance of these components can be increased (so-called Reset operation) or decreased (Set operation) if relatively high electrical quantities (voltage and / or current) are applied. If you simply want to read the value of their resistance without modifying it (Read operation), you must apply relatively small electrical quantities.
    The integration of resistive synapses often takes the form of a memory plane, which is called a "synaptic plane", in which the synapses are arranged in a network with transverse lines and columns which makes it possible to connect a layer of neurons. input (presynaptic neurons) and a layer of output neurons (postsynaptic neurons). Each synapse has a synapse activation terminal and a synaptic signal propagation terminal. The terminals for activating synapses on the same line are linked together via a word line (or “Word-Line”), and the terminals for propagating synapses in the same column are connected between and connected to an artificial neuron via a bit line (or "Bit-Line"). A word line is used to inject a voltage pulse into the synapses of the corresponding line and the bit lines are the outputs of these synapses. In the presence of a presynaptic activation on a word line from a presynaptic neuron, each bit line propagates a current weighted by the value of the corresponding resistive memory to a postynaptic neuron.
    As shown in Figure 1, a resistive memory synapse generally takes the form of a 1T1R cell composed of a variable resistor M and an access transistor T used to regulate the write currents and whose grid forms the activation terminal of the synapse. FIG. 1 shows an example of a synaptic plane with 1T1R cells comprising three word lines WL1-WL3, eight bit lines BL1-BL8 each intended to be connected to an output neuron and a source line (or "Source-Line") SL linked to all synapses. The presence of a transistor by synapse nevertheless limits the density of such a synaptic plane.
    As shown in Figure 2, one can alternatively use 1S1R cells composed of a variable resistor M and a selector S having a behavior similar to a diode, or even two diodes upside down. Each cell
    1S1R is a dipole whose terminals constitute the activation and propagation terminals, and the synaptic plane is organized as represented in FIG. 2 where we have taken the example of a plane comprising three word lines WL1-WL3 and four bit lines BL1-BL4, and where each synapse is taken between a voltage on the corresponding word line and a voltage on its corresponding bit line.
    A number of constraints weigh on the effective implementation of such an artificial neural network.
    For example, if the organization of the synaptic plan has advantages (parallel calculations, density, pooling of pilots), it nevertheless has limitations. First, this organization offers an "all-to-all" connection whereby all presynaptic neurons are connected via a synapse to all postsynaptic neurons. However in certain cases, this “all-to-all” connection can lead to a mainly zero synaptic matrix and therefore to low energy efficiency. This organization also requires having to deal finely with the damaged weights, otherwise we will have a network composed mainly of parasitic synapses, making the analog integration of synaptic weights even more complex.
    Another constraint is linked to the conventional implementation of an artificial neuron in the form of an integrative threshold neuron ("Integrate and Fire" in English). The principle of such an implementation is shown in Figure 3. The contribution V sp ike_ P re of a presynaptic neuron is weighted by the value of the corresponding synaptic resistance R synb and thus provides an excitation current I synb . This current is injected into a capacitor C mem which integrates the various stimulations over time. The membrane voltage, modeled by the voltage V mem across the ability mem C, is compared to a threshold V seu ii · When this threshold is exceeded by the membrane tension, a spike V sp ike is issued and the capacitance C mem is discharged to reset the membrane tension, typically by resetting it.
    [0013]
    However according to Ohm's law, and as represented in figure 4, the current I synb which should depend only on the value of the resistance R synb of the synapse depends in reality on the value of the membrane tension V mem : V ike _ pre - V mem .
    Isynb - synb
    This implies that the higher the voltage V mem , the more the neuron is excited and likely to emit a spike, the less its afferent synapses have an effect on it. Such a phenomenon is problematic. Thus, in a classification layer for example, the neuron supposed to emit the most spikes sees its activity reduced in a greater proportion than that of the less active neurons. Consequently, the difference between this “winning” neuron and the other neurons is reduced.
    Other constraints are linked to the characteristics of RRAM memories. An example of such an RRAM memory is the OxRAM memory which is composed of an insulator wedged between two layers of conductors. During a first stage of formation, a conductive wire grows from one of the conductors towards the other, thus reducing the total resistance of the dipole. Once this wire is formed, the writing actions act on its length to vary the resistance. A Set operation lengthens the wire and reduces the resistance, while a Reset operation has the opposite effect. Reading an OxRAM memory presents a difficulty, that of parasitic writing by gradually changing the value of the resistance over successive readings. To limit this risk, it is advisable to apply a maximum reading voltage of 100 mV. The smallness of this voltage greatly complicates the implementation of an integrative analog reading of these memories. Indeed, the reading voltage V sp ike_ P re limits the membrane voltage V mem , because the membrane capacity C mem is charged through the resistor R synb to which V spi k e _ P re is applied · In other words, the membrane voltage is at most the voltage V spi k e _ P re · Or V mem being an analog calculation element therefore subject in particular to problems of noise, technological variations, capacitive coupling, its voltage range cannot be reduced to a value as low as 100 mV without greatly increasing the sources of calculation errors.
    We also note that RRAMs devices often have a low resistance range (with low values of the order of kQ) and that we can therefore be confronted with time constants of the cut R syn - C mem of the order of a nanosecond or less. However, it is not easy to generate reading pulses of less than 1 ns, except when using a specific circuit. The reading impulse must also be propagated over the entire width of the synaptic plane. The shorter this impulse, the less “clean” it is in the end. Finally, such a pulse is difficult to propagate in active analog circuits responsible for integrating the read current without being confronted with problems of bandwidth and / or distortion. Statement of the invention
    The invention aims to provide a solution to meet one and / or the other of the above constraints. To do this, it proposes an artificial neuron for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight. The artificial neuron has an integration circuit which includes an accumulator of synaptic weights at the terminals of which a membrane tension is established and a comparator configured to emit a postsynaptic pulse if a threshold is crossed by the membrane tension. The artificial neuron further includes a reading circuit configured to impose on the synapse a reading voltage independent of the membrane voltage and to provide the integration circuit with an analog quantity representative of the synaptic weight. Some preferred but non-limiting aspects of this artificial neuron are as follows:
    - the analog quantity representative of the synaptic weight is a voltage;
    the analog quantity representative of the synaptic weight is a voltage independent of the duration of a read pulse;
    the reading circuit comprises a synaptic current accumulator at the terminals of which a voltage is established, the analog quantity is the voltage which is established at the terminals of the synaptic current accumulator and the artificial neuron comprises, between the reading circuit and the integration circuit, a voltage follower circuit configured to copy an addition of the analog quantity and the membrane voltage;
    - the reading circuit is further configured to discharge the synaptic current accumulator before imposing the reading voltage on the synapse;
    the reading circuit comprises a switch having a first terminal intended to be connected to the synapse and a second terminal connected to the integration circuit, and the integration circuit comprises an integrator assembly connected to the second terminal and within which is mounted synaptic weight accumulator;
    - the analog quantity representative of the synaptic weight is a duration.
    - the integration circuit comprises a current source controlled to inject a current into the synaptic weight accumulator during said duration;
    the reading circuit comprises a synaptic current accumulator, a comparator of the voltage across the terminals of the synaptic current accumulator with at least one threshold to provide a comparison result and the artificial neuron comprises, between the reading circuit and the integration circuit, a logic circuit configured to generate, from the result of the comparison, a pulse having said duration;
    the synapse comprising an absolute value memory of synaptic weight and a synaptic weight sign memory, the reading circuit comprises a binary reading circuit of the synaptic weight sign memory and an analog reading circuit of the value memory absolute of synaptic weight M abs controlled by the binary reading circuit;
    - the analog quantity representative of the synaptic weight is a current;
    the reading circuit comprises a current conveyor which comprises an input port X intended to be connected to the synapse, an input port Y intended to be subjected to a fixed voltage and an output port Z connected to the circuit d 'integration;
    - the current conveyor includes a current mirror configured to effect a reduction of the current between the input port X and the output port Z.
    Brief description of the drawings [0019] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of nonlimiting example, and made with reference to the following drawings on which ones :- Figure 5 is a block diagram of an artificial neuron according to the invention;- Figure 6 illustrates an excitatory or inhibitory synapse that can be usedin the context of the invention;- Figure 7 shows the impulse response of the synapse of Figure 6;- Figures 8 and 9 provide examples of integration of the synapse of Figure 6 in a synaptic plane;- Figures 10 and 11 provide another example of excitatory or inhibitory synapse that can be used in the context of the invention;- Figures 12 and 13 are diagrams of artificial neurons according to the invention having a synaptic current accumulator in the reading circuit and a synaptic weight accumulator in the integration circuit and for which the analog quantity representative of the synaptic weight supplied by the read circuit to the integration circuit is a voltage;- Figure 14 shows another neuron according to the invention for which the analog quantity is also a voltage;- Figure 15 shows another neuron according to the invention for which the analog quantity is also a duration;- Figure 16 illustrates another operating mode of the neuron of Figure 15;- Figures 17a, 17b and 19 show circuits for reading a neuron according to the invention for which the analog quantity is a current;- Figure 18 illustrates an alternative embodiment of the read circuits of Figures 17a and 17b. [0020][0021][0022][0023][0024][0025][0026][0027][0028] [fig.l][fig-2][fig.3][fig-4][fig.5][fig.6][fig-7][fig.8][fig.9]
    [Fig. 10]
    [Fig.Π]
    [Fig.12]
    [Fig.13] [0033] [fig. 14]
    [Fig.15]
    [Fig. 16]
    [Fig. 17]
    [Fig.18]
    [Fig. 19]
    [Fig.20]
    Description of the embodiments
    Referring to Figure 5, the invention relates to an artificial neuron NA for neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight.
    The synapse has a terminal for activating the synapse and a terminal for propagating a synaptic signal. In the presence of a presynaptic activation applied to the activation terminal, the propagation terminal propagates a synaptic signal representative of the value of the resistive memory (ie the synaptic weight) towards the artificial neuron NA via a BL bit line.
    The artificial neuron includes an integration circuit CI which includes an accumulator of synaptic weights ACC at the terminals of which a membrane voltage V mem is established and a comparator COMP configured to emit a postsynaptic pulse SO in the event of crossing of a threshold V seu ii by the membrane tension V mem ·
    The invention proposes to decouple the reading of the synaptic weight from its integration while avoiding digitizing the reading of the synaptic weight. The different constraints can thus be distributed according to whether they are inherited from resistive memory technology or from the functioning of the analog neuron. To do this, the invention more particularly proposes that the artificial neuron NA also includes a reading circuit CL configured to impose on the synapse a reading voltage independent of the membrane voltage V mem and to provide the integration circuit CI an analog quantity representative of the synaptic weight PSa.
    The reading circuit CL thus makes it possible to impose on the synapse a reading voltage having an identical polarization for each reading whatever the state of the membrane voltage V mem · This reading circuit also makes it possible to impose at the synapse a reading voltage low enough to avoid any risk of spurious writing. The result of the reading, namely the analog quantity representative of the synaptic weight PSa, is transmitted to the integration circuit. As will be seen below, this quantity can take different forms, such as a voltage, a current, a charge or a duration for example. The integration circuit CI, thus decoupled from the reading, can thus offer a wide range of voltage for the membrane voltage, independent of the specifications of the synapse.
    We detail in the following implementations of resistive synapses which advantageously find application in the context of the invention. It will however be understood that the invention is not limited to these specific implementations.
    We can indeed seek to have synapses which can be both excitatory and inhibitory, and which must therefore be able to both inject and draw current from the neuron. Since the synapses are resistive here and the current they control depends on their resistance, two levels of synapse supply voltage are provided, a positive and a negative. Figure 6 provides an example of such an excitatory and inhibitory synapse, called synapse 2R1C. The synapse comprises an excitatory component CE and an inhibitory component CI arranged in series, with the propagation terminal Bp of the synapse as the midpoint, between a positive supply voltage V read and a negative supply voltage -V read . Each of these components can consist of n> 1 cells 1T1R or 1S1R according to the encoding chosen (in the figure, the reference Select, thus designates the access transistor or the selector of such cells 1T1R or 1S1R). If we use multivalued RRAMs, we can have n = 1. If on the other hand we use binary RRAMs, we predict as many cells as desired weight levels. We can also use synapses equal to -1, 0 or +1, in which case we can use binary RRAMs and n = 1. In any case, reference is made in the following to the total resistance of the cells in parallel by writing R exci and R inhi to designate respectively the total resistance of the excitatory component CE and the total resistance of the inhibitory component CI. In FIG. 6, the capacity Ci oad is part of the reading circuit of a neuron according to a possible embodiment of the invention and is therefore shared by all the synapses of the same column.
    The weight of the synapse is encoded as follows. If we want an exciting synapse, the resistance R inhi is adjusted to its maximum resistance level, while the resistance R e XC i (<Rinhi) modulates the positive weight of the synapse. The lower the resistance R exci , the greater the synaptic weight, since this results in a higher synaptic current. Conversely, if you want an inhibitory synapse, the resistance R exc i is set to its maximum resistance level, while the resistance R inhi (<R exc i) modulates the negative weight of the synapse
    By neglecting the effects of the access selectors or transistors, the diagram composed of the capacity Ci oad and two resistors R inhi and R exci is similar to a damped resistive bridge. By applying the supply voltages V read and -V read , the potential Vi oad at the propagation terminal Bp is then gradually loaded as shown in FIG. 7. This FIG. 7 illustrates that the integration of the synaptic weight cannot be effective than over an integration period PI corresponding to a reading pulse duration less than the time constant of the couple R syn - Ci oad . In the contrary case indeed, with for example R exci “R inhi , one risks obtaining Vi oad = V read whatever the value of R exci .
    This time constant is also even shorter when using binary RRAMs to obtain multivalent synapses, the paralleling of these binary RRAMs resulting in effect in a lower overall resistance. This problem can be circumvented by using a static reading of the synapse, that is to say reading a quantity depending on the weight of the synapse which is stabilized in the sense that it is independent of the duration. of a read pulse. FIG. 7 indeed shows that in the static state reached with a sufficiently long reading pulse, the value of Vi oad can effectively be modulated by the ratio between R exc i and R inhi and therefore by playing with the number of devices in high resistance (“High Resistive State”, HRS) or in low resistance (“Low Resistive State”, LRS) on the excitatory component and inhibitory component side.
    Taking the example of a synapse composed of 8 OxRAM devices, 4 for the excitatory component and 4 for the inhibitory component. With LRS = 3kQ, HRS = 800Ι <Ω and Ci oad = 50 fF , coding on 9 weights (including zero weight) associated with time constants ranging from 1 ns to 250 ps can be obtained. A static reading offers more combinations (13 possible weights) and avoids having to generate short reading pulses. On the other hand, this static reading is more energy-consuming because of the “prolonged” access to the RRAM.
    FIGS. 8 and 9 show a possible organization of the synaptic plane with 2R1C synapses in accordance with that of FIG. 6 in the case where the components CE, CI are respectively based on 1T1R or 1S1R cells.
    In the case 1T1R (Figure 8), the excitatory and inhibitory components participating in the same synapse have their WL activation terminals ; , WLj pooled. Indeed, during the reading phase, the two components are read at the same time. This pooling is welcome because the synaptic plan is complicated by the need to have two distinct source line networks SL a , SL b which are used to distinguish cells with common BL and WL during the writing phase and to polarize the synapses in V read or -V read depending on which encode the excitatory or inhibitory component of their synapse during the read phase. In this configuration, the grids SL a , SL b are intended to remain polarized at ± V read and the write pulses between the ground and V DD are sent to the activation terminals WL ; , WLj. It is noted that the access transistors of the inhibitory cells are reverse biased.
    In the case of 1S1R (FIG. 9), the excitation component of a synapse is taken between a word line WL i exci , WL j exci and a bit line B1 U -B1 X while the inhibiting component of the same synapse is taken between a word line WL i inhi , WL j inhi and the bit line B1 U -B1 X. Read pulses are sent simultaneously on the word lines WL i exci and WL i inhi corresponding to a presynaptic spike pertaining to line i. The word line WL i exci undergoes a mass pulse at V read and the word line WL i inhi undergoes a mass pulse at -V read .
    We can also try to implement negative spikes, namely presynaptic impulses that reverse the weight of the synapse that they trigger.
    Using the example of FIG. 9, instead of sending positive slots on WL ie xci , WL j exci and negative on WL i inhi , WL j inhi , it suffices to reverse these polarizations. Thus, an inhibitory synapse injects a current into Ci oad and conversely an excitatory synapse withdraws from it.
    Using the example of FIG. 8, in the event of a negative spike it is also possible to reverse the polarization of two source lines SL a , SL b . This solution is not necessarily favorable, since it is long and costly in energy because these lines are common to the entire synaptic plane. As a variant, it is possible to use one pilot per source line and the polarization of which is switched from V read to -V read as a function of the sign of the presynaptic pulse to be processed. Consequently, it is no longer necessary to load and unload two complete planes but only the two source lines SL a and SL h which correspond to the synapses excited by the same presynaptic pulse. In this context, it is possible to move the voltage of these source lines only during playback and leave them to ground otherwise. Alternatively, these source lines SL a and SL h can change polarization (from V read to -V read and vice versa) only when necessary by coming to exploit for this purpose a memory in each source line pilot.
    Figures 10 and 11 illustrate another exemplary embodiment for integrating an analog signed weight in a synaptic plane according to which an analog absolute value is associated with a binary sign by means of a synapse called in the following synapse absolute value + sign. The synaptic plane is then more classic, equipped with a single read voltage and having unidirectional read currents. According to this example, a certain number of binary RRAMs, a multivalued RRAM or a single binary RRAM in the event of binary synapse implements (s) the absolute value R abs of synaptic weight while another RRAM, modeled by a resistance R S i gne , is used binary to encode the sign of synaptic weight. This sign RRAM can advantageously be constituted by a triplet or a quintuplet of devices whose sign of the synapse is extracted by majority. The artificial neuron reading circuit then comprises a binary reading circuit Cb of the synaptic weight sign memory M sign and an analog reading circuit Ca of the synaptic weight absolute value memory M abs , said analog reading circuit Ca being controlled by the binary read circuit Cb. The binary reading circuit Cb uses the sign of the presynaptic spike Sp and the sign of the synaptic weight M sign to provide the analog reading circuit Ca with an integration sign Si indicating in which direction to integrate the analog current I abs from the memory of absolute value of synaptic weight M abs . The direction of the analog current I abs being always the same, its inversion in the event of a negative integration sign can be carried out with a simple current mirror as shown in FIG. 11. In this FIG. 11, if the integration sign Si is worth 1, the current I abs is injected into Ci oad . On the other hand, if the sign of integration Si is 0, the current I abs is removed from Ci oad .
    FIGS. 12, 13 and 14 show exemplary embodiments of an artificial neuron according to the invention for which the analog quantity representative of the synaptic weight supplied by the reading circuit to the integration circuit is a voltage . In certain embodiments, the analog magnitude representative of the synaptic weight can be a voltage independent of the duration of a reading pulse, the neurons performing a static reading of the synapse.
    In Figures 12 and 13, the reading circuit CL1 comprises a synaptic current accumulator Ci oad at the terminals of which a voltage Vi oad is established , this voltage corresponding to the analog quantity representative of the synaptic weight. The artificial neuron also comprises a bidirectional voltage follower circuit STI, ST2 interposed between the read circuit CL1 and the integration circuit Cil.
    The functioning of the neuron is as follows. During a reading operation of the synapse, the lower pole of Ci oad is connected to the virtual ground Gnd by a rst_bot switch. In a first phase of the reading operation, Ci oad is first discharged by connecting its upper pole to the virtual ground using a rst_top switch, the reading circuit being thus configured to discharge the accumulator synaptic current Ci oad before imposing the reading voltage on the synapse. The reading of the synapse is then triggered by the opening of the rst_top switch. The current from the bit line BL is then accumulated in Ci oad , generating the read voltage Vi oad . Opening rst_bot provides a floating Vi oad voltage. The voltage follower STI, ST2 is then configured to copy the membrane voltage V mem to the lower terminal of Ci oad . Thus the voltage at the upper limit of C load is worth the addition of V mem and Vi oad . Then the voltage follower STI, ST2 is configured to copy this addition of voltage to the upper limit of the membrane capacity C mem thus providing the new membrane voltage which is compared to the spike emission threshold (s) (s).
    The analog voltage addition proposed in the exemplary embodiments of FIGS. 11 and 12 makes it possible to carry out a static reading of the synapse 2R1C. Dynamic reading is also possible provided that a sufficiently short reading pulse is generated. In these examples, moreover, the maximum stimulation is limited by the reading voltage of the RRAMs. We can then choose that such maximum stimulation alone can trigger a postsynaptic spike by a neuron whose membrane tension is at its resting potential. In which case, the voltage range of the membrane voltage V mem is limited by the read voltage V read . Alternatively, such a stimulation characteristic is not provided, and the membrane tension V mem can be spread over a wider voltage range.
    In Figure 12, the STI voltage follower comprises two operational amplifiers, one intended via the mem2bot switch to copy the membrane voltage to the lower terminal of Ci oad and the other intended via the top2mem switch to copy the addition of voltage to the upper limit of C mem ·
    In FIG. 13, the voltage follower ST2 comprises a single operational amplifier in place of the two operational amplifiers used alternately in FIG. 12. In order to counteract the influence of the parasitic capacitances of the switches during charge transfers to the level of the input of the operational amplifier, an additional capacity Ci oad _ b i S is provided in parallel with the switch rst_bot.
    It will be noted that the synapse absolute value + sign is adapted to the neurons of FIGS. 12 and 13.
    In FIG. 14 which also proposes an analog quantity representative of the synaptic weight in the form of a voltage, the reading circuit CL2 comprises a switch R on / Roff having a first terminal B1 intended to be connected to the synapse via the bit line BL and a second terminal B2 connected to the integration circuit CI2. The integration circuit CI2 includes an integrator assembly connected to the second terminal and within which is mounted the synaptic weight accumulator C mem .
    The reading of the synapse takes place as follows. Initially, the switch is left open (it has a resistance Ropp in its blocked state), the voltage on the bit line V BL stabilizes according to the weight of the synapse (we must therefore have R off »HRS). In a second step, the switch is closed (it has a Ron resistor in its on state), the voltage V BL is integrated by the integrator circuit whose time constant depends on R O n and C mem and not on the LRS of RRAMs . We therefore have R 0N > LRS. The neuron in FIG. 14 thus performs a static reading of the synapse by means of the switch R on / Roff and an integration of the voltage V BL .
    FIGS. 15 and 16 show exemplary embodiments of an artificial neuron according to the invention for which the analog quantity representative of the synaptic weight supplied by the reading circuit to the integration circuit is a duration.
    As for the neurons of FIGS. 12 and 13, the reading circuit CL3 of the neuron shown in FIG. 15 comprises a synaptic current accumulator Ci oad at the terminals of which a voltage Vi oad is established and a rst_load switch making it possible to carry out the discharge of this accumulator before a synaptic weight reading operation. During a reading operation, the accumulator Ci oad is charged by the synaptic current, more or less rapidly depending on the synaptic weight. The duration of this loading can be estimated very simply using an analog comparator. In FIG. 15, we consider both excitatory and inhibitory synapses and we therefore provide two comparators Cp and Cn responsible for comparing the voltage across the synaptic current accumulator terminals Ci oad respectively to a positive threshold Sp and to a negative threshold. On the timing diagrams on the left in FIG. 15, the synapse is exciting and the voltage Vi oad across the terminals of the synaptic current accumulator Ci oad> after it has been discharged, gradually increases until it exceeds the positive threshold Sp and toggle the output Comp_exci of the comparator Cp which thus provides information on the loading time which is representative of the synaptic weight.
    The output Comp_exci of the comparator Cp is supplied to a logic circuit LOG interposed between the read circuit CL3 and the integration circuit CI3. This logic circuit is configured to generate, from the result of the comparison, a voltage pulse having said duration, in this case the pulse Cmd_exci in the example of FIG. 15.
    The integration circuit CI2 for its part comprises a current source SI exc controlled to inject a current into the accumulator of synaptic weights C mem during said duration. The duration of this current injection therefore depends on the value of the synaptic weight, so that the final value of the membrane tension V mem also depends on the value of the synaptic weight.
    In the example shown with excitatory and inhibitory synapses, the integration circuit CI2 comprises another current source SI inhi controlled by a voltage pulse Cmd_inhi to draw current from the synaptic weight accumulator C mem during a duration representative of the synaptic weight.
    The neuron of FIG. 15 can also take into account the sign of the presynaptic spike, the latter Signe_spike being supplied to the logic circuit LOG which is then configured to determine the sign of integration from the sign of the spike and of the sign of the synapse determined by that of the comparators Cp and Cn which switches. This logical and economical treatment of the spike sign allows, particularly in the case of 1T1R cells, to lighten the synaptic plane and its management. It will be noted that the synapse absolute value + sign is particularly suitable for this neuron.
    An advantage of this embodiment is the reliability of the harmful weights. In the case of zero weight, all RRAMs devices in the synapse are at HRS. So, on the one hand, the time constant associated with a zero weight synapse is much more important than the others and, on the other hand, we will have Rexci ~ Rinhi. It is therefore unlikely that the voltage Vi oad crosses one of the two thresholds Sp, Sn not only because it will not have the time but also because its final value is likely to be between the two thresholds. Consequently, the logic circuit LOG sees no switching at the output of the comparators Cp, Cn and does not trigger any charge injection on C mem . A true zero weight which does not in any way modify the state of the neuron is thus implemented.
    FIG. 16 shows timing diagrams illustrating another mode of operation of the neuron of FIG. 15 according to which a double reading is operated so as to be insensitive to the switching times of the comparators Cp, Cn. In fact, according to RRAM technologies and transistors used and the consumption of comparators, it is possible that the switching time T comp of the latter is not negligible compared to the charging time of the accumulator Ci oad . In this case, the duration of the pulse transmitted to the integration circuit may vary little with the value of R syn , which may prove to be detrimental. In this other operating mode, the pulse is generated from two comparator switches. The switching times are thus applied to the start and end of the pulse and therefore do not affect its duration. Thus, at first, the synapse is read in a direction long enough for Vi oad to go abut on V read or -V read according to the sign of the synapse. Then, we reverse the polarization of the reading, the voltage V / oad will therefore cross the potential difference from one polarization of V read to the other and cross the two thresholds Sp, Sn in a time relative to the weight of the synapse . The logic circuit LOG is then configured to generate a voltage pulse between these two comparator switching operations.
    FIGS. 17 to 20 show exemplary embodiments of an artificial neuron according to the invention for which the analog quantity representative of the synaptic weight supplied by the read circuit to the integration circuit is a current. In the examples of FIGS. 17 and 18, the reading circuit CL4, CL5 comprises a current conveyor which has an input port X intended to be connected to the synapse via the bit line, an input port Y intended to be subjected to a fixed voltage (for example ground) for the duration of access to the synapse and an output port Z connected to the integration circuit.
    Such a current conveyor, based on an operational amplifier and two current mirrors, is such that the fixed voltage imposed on the input port Y is copied to the input port X and the current injected into the port input X is reproduced on output port Z (with a sign inversion for the circuit of figure 17, without sign inversion for the circuit of figure 18). A fixed voltage being imposed on the Y port, we just slave the bit line voltage to this fixed voltage (it is thus independent of the membrane voltage of the neuron) and debit the synaptic current on the output port Z. This synaptic current is supplied to the integration circuit which will then carry out an analog integration.
    The time constant R syn -C mem may however prove to be too short for the operational amplifier and the current mirrors composing the current conveyor to function correctly. Thus, in an alternative embodiment, the current conveyor comprises, as shown in FIG. 19, a current mirror configured to effect a reduction in the current between the input port X and the output port Z. In this figure, we actually has T ~ Iin, with K a factor 1 out ~ K greater than 1 which allows the use of longer reading pulses and therefore more suited to the operation of the active elements without saturating the membrane capacity.
    In an alternative embodiment shown in Figure 20, the neuron includes a transmission gate T between the read circuit and the integration circuit. This gate makes it possible to dissociate the access time to the RRAMs and the integration time, which makes it possible to wait for the voltage on the input port X to stabilize before integrating the reading current and to play with a brief integration pulse without requiring a particularly reactive operational amplifier.
    Furthermore, in this figure 20 the reading circuit CL6 advantageously comprises both the reversing current mirror of the reading circuit CL4 and the non-reversing current mirror of the reading circuit CL5 (these mirrors being able to achieve a lowering of the current in accordance with FIG. 19) and a selector S controlled by a signal Signe_spike representative of the sign of the presynaptic spike to come and select the output of one or the other of these current mirrors.
    The invention is not limited to the above-described artificial neuron, but extends to a neuromorphic chip comprising a plurality of resistive memory synapses arranged in a network with transverse lines and columns. Each synapse has a propagation terminal, the propagation terminals of the synapses of the same column being linked together and connected to an artificial neuron according to the invention. The synapses can be excitatory or inhibitory synapses such as those presented previously in connection with FIGS. 6 to 11.
    权利要求:
    Claims (1)
    [1" id="c-fr-0001]
    Claims [Claim 1] Artificial neuron (NA) for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight, the artificial neuron comprising an integration circuit (CI, C11, CI2, CI3) which comprises a synaptic weight accumulator (ACC, C mem ) at the terminals of which a membrane tension is established (V mem ) and a comparator (COMP) configured to emit a postsynaptic pulse in the event of a threshold being crossed by the membrane tension, the artificial neuron being characterized in that '' it further comprises a reading circuit (CL, CL1, CL2, CL3, CL4, CL5) configured to impose on the synapse a reading voltage independent of the membrane voltage and to provide the integration circuit with a representative analog quantity synaptic weight (PSa). [Claim 2] An artificial neuron according to claim 1, in which the analog quantity representative of the synaptic weight is a voltage. [Claim 3] An artificial neuron according to claim 2, in which the analog quantity representative of the synaptic weight is a voltage independent of the duration of a reading pulse. [Claim 4] Artificial neuron according to either of Claims 2 and 3, in which the reading circuit (CL1) comprises a synaptic current accumulator (Cioad) at the terminals of which a voltage is established, the analog quantity is the voltage which is established at terminals of the synaptic current accumulator and the artificial neuron comprises, between the reading circuit and the integration circuit, a voltage follower circuit (STI, ST2) configured to copy an addition of the analog quantity and the voltage membrane. [Claim 5] The artificial neuron of claim 4, wherein the read circuit is further configured to discharge the synaptic current accumulator (Ci oad ) before imposing the read voltage on the synapse. [Claim 6] Artificial neuron according to claim 3, in which the read circuit (CL2) comprises a switch (R on / Roff) having a first terminal (Bl) intended to be connected to the synapse and a second terminal (B2) connected to the circuit d integration (CI2), and in which the integration circuit comprises an integrator assembly connected to the second terminal and within which is mounted the synaptic weight accumulator (C mem ). [Claim 7] An artificial neuron according to claim 1, wherein the magnitude
    analog representative of the synaptic weight is a duration. [Claim 8] An artificial neuron according to claim 7, in which the integration circuit (CI3) comprises a current source (SI exc , SI inhi ) controlled to inject a current into the synaptic weight accumulator during said duration. [Claim 9] Artificial neuron according to claim 8, in which the reading circuit (CL3) comprises a synaptic current accumulator (Ci oad ), a comparator (Cp, Cn) of the voltage across the synaptic current accumulator with at least one threshold (Sp, Sn) for providing a comparison result and the artificial neuron comprises a logic circuit (LOG) interposed between the read circuit and the integration circuit, the logic circuit being configured to generate, from the result of the comparison, a pulse (Cmd_exci, Cmd_inhi) presenting said duration. [Claim 10] Artificial neuron according to one of Claims 4, 5 or 9, in which, the synapse comprising an absolute value memory of synaptic weight (M abs ) and a synaptic weight sign memory (M sign ), the reading circuit comprises a binary reading circuit (Cb) of the synaptic weight sign memory and an analog reading circuit (Ca) of the synaptic weight absolute value memory M abs controlled by the binary reading circuit. [Claim 11] An artificial neuron according to claim 1, in which the analog quantity representative of the synaptic weight is a current. [Claim 12] Artificial neuron according to claim 11, in which the reading circuit (CL4, CL5) comprises a current conveyor which comprises an input port X intended to be connected to the synapse, an input port Y intended to be imposed a fixed voltage and an output port Z connected to the integration circuit. [Claim 13] An artificial neuron according to claim 12, wherein the current conveyor comprises a current mirror configured to effect a lowering of the current between the input port X and the output port Z. [Claim 14] Neuromorphic chip comprising a plurality of resistive memory synapses arranged in a network with transverse lines and columns, each synapse having a propagation terminal of a synaptic signal, the propagation terminals of synapses of the same column being interconnected and connected to an artificial neuron according to one of claims 1 to 13. [Claim 15] The neuromorphic chip of claim 14, wherein each
    synapse comprises an excitatory component and an inhibitory component connected in series by the propagation terminal of the synapse.
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    同族专利:
    公开号 | 公开日
    FR3089663B1|2021-09-17|
    US20200202206A1|2020-06-25|
    EP3663988A1|2020-06-10|
    引用文献:
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    US20180260696A1|2017-03-08|2018-09-13|Arm Ltd|Spiking neural network|
    WO2018201060A1|2017-04-27|2018-11-01|The Regents Of The University Of California|Mixed signal neuromorphic computing with nonvolatile memory devices|
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    法律状态:
    2019-12-31| PLFP| Fee payment|Year of fee payment: 2 |
    2020-06-12| PLSC| Publication of the preliminary search report|Effective date: 20200612 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 3 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1872515A|FR3089663B1|2018-12-07|2018-12-07|Artificial neuron for neuromorphic chip with resistive synapses|FR1872515A| FR3089663B1|2018-12-07|2018-12-07|Artificial neuron for neuromorphic chip with resistive synapses|
    EP19212046.7A| EP3663988A1|2018-12-07|2019-11-28|Artificial neuron for neuromorphic chip with resistive synapses|
    US16/703,465| US20200202206A1|2018-12-07|2019-12-04|Artificial neuron for neuromorphic chip with resistive synapses|
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